? 1999 fairchild semiconductor corporation ds500021 www.fairchildsemi.com june 1997 revised december 1999 FST3244 octal bus switch FST3244 octal bus switch general description the fairchild switch FST3244 provides 8-bits of high- speed cmos ttl-compatible bus switching in a standard '244 pin-out. the low on resistance of the switch allows inputs to be connected to outputs without adding propaga- tion delay or generating additional ground bounce noise. the device is organized as two 4-bit switches with separate oe inputs. when oe is low, the switch is on and port a is connected to port b. when oe is high, the switch is open and a high-impedance state exists between the two ports. features n 4 w switch connection between two ports. n minimal propagation delay through the switch. n low l cc . n zero bounce in flow-through mode. n control inputs compatible with ttl level. ordering code: devices also available in tape and reel. specify by appending the suffix letter x to the ordering code. logic diagram pin descriptions connection diagram truth table order number package number package description FST3244wm m20b 20-lead small outline integrated circuit (soic), jedec ms-013, 0.300 wide FST3244qsc mqa20 20-lead quarter size outline package (qsop), jedec mo-137, 0.150 wide FST3244mtc mtc20 20-lead thin shrink small outline package (tssop), jedec mo-153, 4.4mm wide pin name description oe 1 , oe 2 bus switch enable 1a, 2a bus a 1b, 2b bus b inputs inputs/outputs oe 1 oe 2 1a, 1b 2a, 2b ll1a = 1b 2a = 2b lh1a = 1b z hlz2a = 2b hhz z
www.fairchildsemi.com 2 FST3244 absolute maximum ratings (note 1) recommended operating conditions (note 3) note 1: the absolute maximum ratings are those values beyond which the safety of the device cannot be guaranteed. the device should not be operated at these limits. the parametric values defined in the electrical characteristics tables are not guaranteed at the absolute maximum rating. the recommended operating conditions tables will define the conditions for actual device operation. note 2: the input and output negative voltage ratings may be exceeded if the input and output diode current ratings are observed. note 3: unused control inputs must be held high or low. they may not float. dc electrical characteristics note 4: typical values are at v cc = 5.0v and t a = + 25 c note 5: measured by the voltage drop between a and b pins at the indicated current through the switch. on resistance is determined by t he lower of the voltages on the two (a or b) pins. supply voltage (v cc ) - 0.5v to + 7.0v dc switch voltage (v s ) - 0.5v to + 7.0v dc input voltage (v in ) (note 2) - 0.5v to + 7.0v dc input diode current (l ik ) v in < 0v - 50ma dc output (i out ) sink current 128ma dc v cc /gnd current (i cc /i gnd ) + / - 100ma storage temperature range (t stg ) - 65 c to + 150 c power supply operating (v cc ) 4.0v to 5.5v input voltage (v in )0v to 5.5v output voltage (v out )0v to 5.5v input rise and fall time (t r , t f ) switch control input 0ns/v to 5ns/v switch i/o 0ns/v to dc free air operating temperature (t a ) - 40 c to + 85 c symbol parameter v cc (v) t a = - 40 c to + 85 c units conditions min typ (note 4) max v ik clamp diode voltage 4.5 - 1.2 v i in = - 18ma v ih high level input voltage 4.0C5.5 2.0 v v il low level input voltage 4.0C5.5 0.8 v i i input leakage current 5.5 1.0 m a0 v in 5.5v i oz off-state leakage current 5.5 1.0 m a0 a, b v cc r on switch on resistance 4.5 4 7 w v in = 0v, i in = 64ma (note 5) 4.5 4 7 w v in = 0v, i in = 30ma 4.5 8 15 w v in = 2.4v, i in = 15ma 4.0 11 20 w v in = 2.4v, i in = 15ma i cc quiescent supply current 5.5 3 m av in = v cc or gnd, i out = 0 d i cc increase in i cc per input 5.5 2.5 ma one input at 3.4v other inputs at v cc or gnd
3 www.fairchildsemi.com FST3244 ac electrical characteristics note 6: this parameter is guaranteed by design but is not tested. the bus switch contributes no propagation delay other than the rc del ay of the typical on resistance of the switch and the 50pf load capacitance, when driven by an ideal voltage the source (zero output impedance). capacitance (note 7) note 7: t a = + 25 c, f = 1 mhz, capacitance is characterized but not tested. ac loading and waveforms note: input driven by 50 w source terminated in 50 w note: c l includes load and stray capacitance note: input prr = 1.0 mhz, t w = 500 ns figure 1. ac test circuit figure 2. ac waveforms symbol parameter t a = - 40 c to + 85 c, c l = 50pf, ru = rd = 500 w units conditions figure no. v cc = 4.5 C 5.5v v cc = 4.0v min max min max t phl ,t plh prop delay bus to bus(note 6) 0.25 0.25 ns v i = open figure 1 figure 2 t pzh , t pzl output enable time 1.0 5.6 6.1 ns v i = 7v for t pzl figure 1 figure 2 v i = open for t pzh t phz , t plz output disable time 1.0 6.2 5.6 ns v i = 7v for t plz figure 1 figure 2 v i = open for t phz symbol parameter typ max units conditions c in control pin input capacitance 3 pf v cc = 5.0v c i/o input/output capacitance 5 pf v cc , oe = 5.0v
www.fairchildsemi.com 4 FST3244 physical dimensions inches (millimeters) unless otherwise noted 20-lead small outline integrated circuit (soic), jedec ms-013, 0.300 wide package number m20b 20-lead quarter size outline package (qsop), jedec mo-137, 0.150 wide package number mqa20
5 www.fairchildsemi.com FST3244 octal bus switch physical dimensions inches (millimeters) unless otherwise noted (continued) 20-lead thin shrink small outline package (tssop), jedec mo-153, 4.4mm wide package number mtc20 technology description the fairchild switch family derives from and embodies fairchilds proven switch technology used for several years in its 74lvx3l384 (fst3384) bus switch product. fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and fairchild reserves the right at any time without notice to change said circuitry and specifications. life support policy fairchilds products are not authorized for use as critical components in life support devices or systems without the express written approval of the president of fairchild semiconductor corporation. as used herein: 1. life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be rea- sonably expected to result in a significant injury to the user. 2. a critical component in any component of a life support device or system whose failure to perform can be rea- sonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com
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